华东师范大学学报(自然科学版) ›› 2006, Vol. 2006 ›› Issue (4): 11-15.

• 物理学 电子科学技术 • 上一篇    下一篇

基于Spartan II XC2S100的I2C总线通信

胡文静1,2, 李外云1, 刘锦高1   

  1. 1.华东师范大学 信息科学与技术学院, 上海 200062； 2.湖南理工学院 物理与电子信息系, 湖南 岳阳 414006
  • 收稿日期:2004-10-26 修回日期:2004-12-30 出版日期:2006-07-25 发布日期:2006-07-25
  • 通讯作者: 刘锦高

Design of I2CBus Interface Based on Spartan II XC2S100(Chinese)

HU Wen-jing1,2, LI Wai-yun1, LIU Jing-gao1   

  1. 1.School of Information Science and Technology, East China Normal University, Shanghai 200062,China; 2.Department of Physics and Electronics Information, Hunan Institute of Science and Technology, Yueyang Hunan 414006,China
  • Received:2004-10-26 Revised:2004-12-30 Online:2006-07-25 Published:2006-07-25
  • Contact: LIU Jing-gao

摘要： 介绍了I2C总线协议及基于FPGA芯片的I2C总线接口结构框图.提出了复杂时序电路状态机嵌套的设计思想，并给出了基于Verilog HDL的I2C总线接口电路的硬件描述.在ISE 6.1i平台下结合ModelSim SE 5.7进行了设计仿真，实现了XC2S100对I2C总线器件的读写操作.

关键词: 现场可编程门阵列(FPGA), XC2S100, I2C总线, Verilog HDL, 状态机嵌套, 现场可编程门阵列(FPGA), XC2S100, I2C总线, Verilog HDL, 状态机嵌套

Abstract: The protocol and principle of I2C-Bus were introduced. The framework of I2CBus based on FPGA was proposed. The idea of nesting state-machine of complicated timing-circuit and the hardware description of I2C-Bus interface by Verilog HDL were presented. The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I2C device based on Spartan II XC2S100 was implemented.

Key words: XC2S100, I2C-Bus, Verilog HDL, nesting state machine, Field Programmable Gate Array, XC2S100, I2C-Bus, Verilog HDL, nesting state machine

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