面向边缘计算的CMOS高能效芯片跨层级设计与多场景优化方法

doi:10.3969/j.issn.1000-5641.2026.02.018

摘要/Abstract

摘要：

随着集成电路工艺逐步进入后摩尔时代, 单纯依赖晶体管尺寸微缩所带来的性能与能效提升已难以持续, 能效问题正日益成为制约芯片性能提升和应用扩展的关键因素. 尤其在以边缘计算为代表的新兴应用场景中, 受限于功耗预算、面积成本与实时性要求, 芯片设计面临更加严苛且多样化的约束条件. 在此背景下, 先进互补金属氧化物半导体 (Complementary Metal-Oxide-Semiconductor, CMOS) 芯片设计的优化重心正由以工艺演进为主, 转向以电路、架构与系统层面协同优化为核心的设计驱动路径. 本文围绕面向边缘计算的CMOS高能效芯片设计与优化问题, 系统综述了设计层面的关键技术与方法体系. 首先, 从后摩尔时代的技术背景出发, 分析了能效瓶颈的内在成因及其在低功耗场景下的表现特征. 随后, 按照电路层、架构层以及新兴计算范式的组织逻辑, 系统梳理了支撑高能效边缘计算的关键设计方法. 在此基础上, 结合人工智能推理、边缘智能与物联网以及通信与信号处理等典型边缘应用场景, 深入分析了不同应用约束下能效瓶颈的形成机理及相应的设计权衡策略. 最后, 本文总结了面向边缘计算的高能效CMOS芯片设计所面临的关键挑战, 并对未来发展趋势进行了展望, 旨在为后摩尔时代复杂应用约束下的高能效边缘计算芯片设计提供系统性的技术参考与思路借鉴.

关键词: CMOS高能效芯片, 边缘计算, 能效优化, 设计驱动, 体系结构优化, 新兴计算范式

Abstract:

As integrated circuit technologies progressively enter the post-Moore era, performance and energy-efficiency improvements achieved solely through transistor scaling have become increasingly difficult to sustain. Energy efficiency has thus emerged as a critical factor limiting further performance scaling and application deployment. In particular, for emerging application scenarios represented by edge computing, chip design is subject to more stringent and diverse constraints due to tight power budgets, area costs, and real-time requirements. Under these conditions, the optimization focus of advanced Complementary Metal-Oxide-Semiconductor (CMOS) chip design is shifting from process-centric scaling toward a design-driven paradigm that emphasizes cross-layer coordinated optimization across the circuit, architecture, and system levels. This paper presents a systematic and application-oriented review of key techniques and methodological frameworks for CMOS high-energy-efficiency chip design targeting edge computing. First, from the perspective of the post-Moore technological context, the intrinsic causes of energy-efficiency bottlenecks and their manifestations under low-power constraints are analyzed. Subsequently, following a cross-layer organizational hierarchy spanning the circuit level, the architectural level, and emerging computing paradigms, representative design methodologies enabling high-energy-efficiency edge computing are comprehensively reviewed, with emphasis on their underlying energy-efficiency mechanisms and design trade-offs. Building on this foundation, multiple representative edge application scenarios—including artificial intelligence inference, edge intelligence and the Internet of Things, as well as communication and signal processing—are examined to elucidate how application-specific constraints give rise to distinct energy-efficiency bottlenecks and corresponding optimization strategies. Finally, the major challenges facing CMOS high-energy-efficiency chip design for edge computing are summarized, and future research trends are discussed, with the aim of providing cross-layer design insights and systematic methodological references for high-energy-efficiency edge computing chip design under complex post-Moore application constraints.

Key words: CMOS high-energy-efficiency chips, edge computing, energy-efficiency optimization, design-driven methodology, architectural optimization, emerging computing paradigms

中图分类号:

TN47

王旭, 陈珂, 王成华, 刘伟强. 面向边缘计算的CMOS高能效芯片跨层级设计与多场景优化方法[J]. 华东师范大学学报（自然科学版）, 2026, 2026(2): 199-213.

Xu WANG, Ke CHEN, Chenghua WANG, Weiqiang LIU. Cross-layer design and multi-scenario optimization methods for CMOS high-energy-efficiency edge computing chips[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 199-213.

图/表 6

图1

图2

图3

图4

图5

表1

参考文献 45

1	LEISERSON C E, THOMPSON N C, EMER J S, et al.. There’s plenty of room at the Top: What will drive computer performance after Moore’s Law?. Science, 2020, 368 (6495): eaam9744.
2	ROTHE R, LI H, NIKONOV D E, et al.. Energy efficient logic and memory design with beyond-CMOS magnetoelectric spin–orbit (MESO) technology toward ultralow supply voltage. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023, 9 (2): 124- 133.
3	LI Y H, LI X Z, ZHAO Z Y, et al.. Momentum-dependent field-effect transistor. Science Advances, 2025, 11 (27): eadv4742.
4	LIU W Q, LOMBARDI F. Approximate Computing [M]. Cham: Springer International Publishing, 2022.
5	LIU W Q, LOMBARDI F, SCHULTE M.. Approximate computing: From circuits to applications [scanning the issue]. Proceedings of the IEEE, 2020, 108 (12): 2103- 2107.
6	EAMANI R R, VINODHKUMAR N, HARRISON A, et al.. FPGA-based design of ultra-efficient approximate adders for high-fidelity image processing: A logic-optimized approach. Engineering Reports, 2025, 7 (7): e70262.
7	CHEN K, GAO Y, WARIS H, et al.. Approximate softmax functions for energy-efficient deep neural networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31 (1): 4- 16.
8	WANG H N, CHEN K, YAN C G, et al. Hardware-efficient accurate and approximate FPGA multipliers for error-tolerant applications [C]// 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2023: 977-981.
9	UYTTERHOEVEN R, DEHAENE W.. Design margin reduction through completion detection in a 28-nm near-threshold DSP processor. IEEE Journal of Solid-State Circuits, 2022, 57 (2): 651- 660.
10	WANG X L, LIU X S, KI W H.. A self-clocked and variation-tolerant unified voltage-and-frequency regulator for in-order executed digital loads. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70 (11): 4627- 4640.
11	XIONG W, CAO J C, LIU Y Z, et al.. A reliable and efficient online solution for adaptive voltage and frequency scaling on FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32 (6): 1058- 1071.
12	姚蔓婷, 邱源, 柳宜川, 等.. 高层综合中面向运算器电源门控技术的低能耗调度算法. 华东理工大学学报(自然科学版), 2022, 48 (4): 543- 548.
13	CHENG W K, YEH Z M, KAO H Y, et al.. Cross-mesh clock network synthesis. Electronics, 2023, 12 (16): 3410.
14	ASHOK KUMAR C, MADHAVI B K, KISHORE K L. Enhanced clock gating technique for power optimization in SRAM and sequential circuit [J]. Journal of Automation, Mobile Robotics and Intelligent Systems, 2022: 32-38.
15	RAFIQ M, KAUR T, GAIDHANE A, et al.. Ferroelectric FET-based time-mode multiply-accumulate accelerator: Design and analysis. IEEE Transactions on Electron Devices, 2023, 70 (12): 6613- 6621.
16	LEE D U. Tutorial: HBM DRAM and 3D stacked memory [C]// 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2022: 1-113.
17	ZHOU H B, LI S F, ANG K W, et al.. Recent advances in in-memory computing: Exploring memristor and memtransistor arrays with 2D materials. Nano-Micro Letters, 2024, 16, 121.
18	WANG C Y, SHI G, QIAO F, et al.. Research progress in architecture and application of RRAM with computing-in-memory. Nanoscale Advances, 2023, 5 (6): 1559- 1573.
19	NOWSHIN F, HUANG Y, SARKAR M R, et al.. MERRC: A memristor-enabled reconfigurable low-power reservoir computing architecture at the edge. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71 (1): 174- 186.
20	李超, 张彬, 万俊, 等.. 粗粒度可重构技术综述. 数字技术与应用, 2025, 43 (4): 161- 167.
21	ZHOU P J, YU Q, CHEN M, et al. A 0.96pJ/SOP, 30.23K-neuron/mm2 heterogeneous neuromorphic chip with fullerene-like interconnection topology for edge-AI computing [C]// 2024 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2024: 1-5.
22	TEWARI A, JHA S S, SNEH A, et al.. Reconfigurable radar signal processing accelerator for integrated sensing and communication system. IEEE Transactions on Aerospace and Electronic Systems, 2024, 61 (1): 162- 181.
23	BHATTACHARYA S, RAO V S. Multi-chiplet heterogeneous integration packaging for semiconductor system scaling [C]// 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2023: 1-4.
24	WANG B, CHEN G, FOO L Y, et al. Signal and power integrity design of advanced interface bus (AIB) for FPGA packages [C]// 2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2023: 1-3.
25	WUU J, AGARWAL R, CIRAULA M, et al. 3D V-cache: The implementation of a hybrid-bonded 64MB stacked cache for a 7nm x86-64 CPU [C]// 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2022: 428-429.
26	RATHI N, AGRAWAL A, LEE C, et al. Exploring spike-based learning for neuromorphic computing: Prospects and perspectives [C]// 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021: 902-907.
27	KHODAGHOLY D, GELINAS J N, THESEN T, et al.. NeuroGrid: Recording action potentials from the surface of the brain. Nature Neuroscience, 2015, 18 (2): 310- 315.
28	CHIU Y C, KHWA W S, YANG C S, et al.. A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices. Nature Electronics, 2023, 6 (7): 534- 543.
29	PAINKRAS E, PLANA L A, GARSIDE J, et al.. SpiNNaker: A 1-W 18-core system-on-chip for massively-parallel neural network simulation. IEEE Journal of Solid-State Circuits, 2013, 48 (8): 1943- 1953.
30	CHANG C Y, CHUANG Y C, HUANG C T, et al.. Recent progress and development of hyperdimensional computing (HDC) for edge intelligence. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023, 13 (1): 119- 136.
31	AMROUCH H, IMANI M, JIAO X, et al. Brain-inspired hyperdimensional computing for ultra-efficient edge AI [C]// 2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS). IEEE, 2022: 25-34.
32	GE L L, PARHI K K.. Classification using hyperdimensional computing: A review. IEEE Circuits and Systems Magazine, 2020, 20 (2): 30- 47.
33	IMANI M, BOSCH S, DATTA S, et al.. QuantHD: A quantization framework for hyperdimensional computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (10): 2268- 2278.
34	LIU Y D, LIU S T, WANG Y Z, et al.. A survey of stochastic computing neural networks for machine learning applications. IEEE Transactions on Neural Networks and Learning Systems, 2021, 32 (7): 2809- 2824.
35	ALAWAD M, LIN M J.. Survey of stochastic-based computation paradigms. IEEE Transactions on Emerging Topics in Computing, 2019, 7 (1): 98- 114.
36	JIAO Y R, ZHAO H, TANG J S, et al.. A memristor-based energy-efficient compressed sensing accelerator with hardware–software co-optimization for edge computing. National Science Review, 2025, 13 (1): nwaf499.
37	HU J X, LI B Z, MA C, et al.. Spin-hall-effect-based stochastic number generator for parallel stochastic computing. IEEE Transactions on Electron Devices, 2019, 66 (8): 3620- 3627.
38	LAMMIE C, ESHRAGHIAN J K, LU W D, et al.. Memristive stochastic computing for deep learning parameter optimization. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68 (5): 1650- 1654.
39	CHOQUETTE J.. NVIDIA hopper H100 GPU: Scaling performance. IEEE Micro, 2023, 43 (3): 9- 17.
40	QIAN J Y, GE H T, LU Y C, et al.. A 4.69-TOPS/W training, 2.34-μJ/image inference on-chip training accelerator with inference-compatible backpropagation and design space exploration in 28-nm CMOS. IEEE Journal of Solid-State Circuits, 2025, 60 (1): 298- 307.
41	王涛. 低功耗电源管理系统研究与设计 [D]. 上海: 华东师范大学, 2022.
42	XU K R, ZHANG H W, LI Y S, et al.. An ultra-low power TinyML system for real-time visual processing at edge. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70 (7): 2640- 2644.
43	SCHIAVONE P D, ROSSI D, DI MAURO A, et al.. Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29 (4): 677- 690.
44	CHOI J, PARK J, LEE N.. Energy efficiency maximization precoding for quantized massive MIMO systems. IEEE Transactions on Wireless Communications, 2022, 21 (9): 6803- 6817.
45	ARDA S E, KRISHNAKUMAR A, GOKSOY A A, et al.. DS3: A system-level domain-specific system-on-chip simulation framework. IEEE Transactions on Computers, 2020, 69 (8): 1248- 1262.

技术层级	主要特点	能效优势	主要挑战	能效水平
电路层	放松精度与电压裕量, 进行细粒度调节	直接降低开关功耗与泄漏功耗	对 PVT 波动敏感, 可靠性受限	近阈值DSP(28 nm): 16 GOPS、 80 GOPS/W^[9]
架构层	重组计算与存储关系, 减少数据搬运	显著降低存储访问能耗	架构与应用强相关	IBM HERMES: 63.11 TOPS、 9.76 TOPS/W
新兴计算范式	事件驱动或非传统数据表示	利用稀疏性实现超低平均功耗	算法与工具链不成熟	SpiNNaker2: 2.24 TOPS、 2.13 TOPS/W
跨层协同设计方法	算法–架构–电路联合优化	系统级能效显著提升	设计空间大、流程复杂	Google TPU v1: 86 TOPS、 2.15 TOPS/W