华东师范大学学报(自然科学版) ›› 2026, Vol. 2026 ›› Issue (2): 59-70.doi: 10.3969/j.issn.1000-5641.2026.02.006

• 射频前端与毫米波集成电路 • 上一篇    下一篇

一款20~25 GHz基于变压器的改进型多路径噪声抵消低噪声放大器

王梓尧, 卢禹日, 张润曦*()   

  1. 华东师范大学 微电子电路与系统研究所, 上海 200241
  • 收稿日期:2025-12-24 出版日期:2026-03-25 发布日期:2026-04-03
  • 通讯作者: 张润曦 E-mail:rxzhang@ee.ecnu.edu.cn
  • 基金资助:
    上海市科委资助项目(22DZ2229004)

A 20~25 GHz transformer-based improved multi-path noise-canceling low noise amplifier

Ziyao WANG, Yuri LU, Runxi ZHANG*()   

  1. Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai 200241, China
  • Received:2025-12-24 Online:2026-03-25 Published:2026-04-03
  • Contact: Runxi ZHANG E-mail:rxzhang@ee.ecnu.edu.cn

摘要:

提出了一种20~25 GHz低噪声放大器, 该放大器采用基于变压器的改进型多路径噪声抵消(IMNC)结构. 所提出的IMNC方法解决了传统双路径噪声抵消(DPNC)技术的关键局限性. DPNC技术使用共源(CS)级和共栅(CG)级来相互抵消噪声, 但是并不能完全消除CG级的噪声. 尽管增加CG晶体管的跨导可以改善CS级的噪声消除, 但它引入了功耗和噪声性能之间的权衡. 为了克服这些限制, IMNC架构引入了一个无源网络, 即3圈堆叠变压器, 使得CG级增益提高, 在不增加功耗的情况下改善了CS级的噪声抵消效果. 该变压器还构建了一个额外的噪声传输路径, 使部分CG级噪声能够实现自抵消. 与传统的DPNC方法相比, 这些改进带来了更好的噪声性能和功率效率. 本文采用40 nm 互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)工艺制造, 峰值增益为14.5 dB, 3 dB带宽为5.1 GHz(在20~25 GHz频段), 最小噪声系数(Noise Figure, NF)为2.0 dB, 功耗为22.4 mW, 核心面积为0.16 mm2.

关键词: 互补金属氧化物半导体, 低噪声放大器, 噪声抵消, 跨导增强

Abstract:

This paper presents a 20~25 GHz low noise amplifier that employs a transformer-based improved multi-path noise-canceling (IMNC) architecture. The proposed IMNC approach addresses key limitations of the conventional dual-path noise-canceling (DPNC) technique that employs common-source (CS) and common-gate (CG) stages to suppress each other's noise. In DPNC designs, noise from the CG stage cannot be fully canceled, and increasing CG transconductance to enhance CS-stage noise suppression results in a tradeoff between noise performance and power consumption. To overcome these limitations, the proposed IMNC architecture introduces a three-coil transformer that passively boosts the gain of the CG stage, thereby improving CS-stage noise cancellation without additional power consumption. The transformer also provides an additional noise-canceling path that enables partial self-cancellation of CG stage noise. These improvements lead to better noise performance and power efficiency compared to the conventional DPNC approach. Fabricated in a 40 nm complementary metal oxide semiconductor (CMOS) process, the proposed low noise amplifier achieves a peak gain of 14.5 dB, a 3 dB bandwidth of 5.1 GHz spanning 20 to 25 GHz, and a minimum noise figure (NF) of 2.0 dB, while consuming 22.4 mW of power and occupying a core area of 0.16 mm2.

Key words: complementary metal oxide semiconductor (CMOS), low noise amplifier, noise cancellation, transconductance boosting

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