基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器设计

doi:10.3969/j.issn.1000-5641.2026.02.010

华东师范大学学报（自然科学版） ›› 2026, Vol. 2026 ›› Issue (2): 108-116.doi: 10.3969/j.issn.1000-5641.2026.02.010

• 电源管理与数据转换器 • 上一篇

基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器设计

韩守祥, 蒲俊豪, 胡治伟, 张润曦*()

华东师范大学微电子电路与系统研究所, 上海　200241

收稿日期:2025-09-05 接受日期:2025-12-13 出版日期:2026-03-25 发布日期:2026-04-03
通讯作者: 张润曦 E-mail:rxzhang@ee.ecnu.edu.cn
基金资助:
上海东方英才青年项目 (15904-412214-24013); 上海市科委资助项目 (22DZ2229004)

High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier

Shouxiang HAN, Junhao PU, Zhiwei HU, Runxi ZHANG*()

Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai　200241, China

Received:2025-09-05 Accepted:2025-12-13 Online:2026-03-25 Published:2026-04-03
Contact: Runxi ZHANG E-mail:rxzhang@ee.ecnu.edu.cn

摘要/Abstract

摘要：

针对5G和WiFi 6E的无线通信应用场景, 提出了一款基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器(Pipeline SAR ADC). 针对传统流水线ADC中残差放大器速度慢、功耗高的问题, 设计了一种基于自偏置环形放大器的伪差分开关电容放大器, 采用第二级参考电压减半的方式, 减小系统功耗, 提高整体工作速度. 针对传统栅压自举开关, 进行速度优化和时钟馈通补偿. 提出了一种基于SR-latched的数据寄存器, 提高了SAR ADC逻辑电路的速度. 该ADC采用55 nm CMOS工艺设计, 核心面积为0.182 mm². 芯片后仿真结果表明: 在27℃下, 电源电压为1.2 V时, 输入信号频率为97.85 MHz时, 信噪失真比(SNDR)为72.93 dB, 功耗为9.28 mW, 品质因数FoM_S为173.25 dB.

关键词: 流水线型模数转换器, 逐次逼近型模数转换器, 环形放大器, 数据寄存器

Abstract:

This study proposes a 12b 200 MS/s pipeline successive approximation analog-to-digital converter (Pipeline SAR ADC) for 5G and Wi-Fi 6E wireless communication applications. To address drawbacks such as slow speed and high power consumption in the residue amplifiers of conventional Pipeline ADC, a pseudo-differential switched-capacitor amplifier based on a self-biased ring amplifier is designed. This design incorporates a reference voltage-halving technique in the second stage to reduce the system power consumption and enhance the overall speed. For traditional gate-bootstrapped switches, optimizations for speed and partial compensation of clock feedthrough effects are implemented. In addition, a set-reset (SR) latched data register is proposed to accelerate the logic circuitry of the SAR ADC. The ADC is designed using a 55 nm CMOS process with a core area of 0.182 mm². The simulation results show that at 27℃ and a 1.2 V supply voltage, the signal-to-noise distortion ratio (SNDR) was 72.93 dB, the power consumption was 9.28 mW, and the Schreier figure of merit (FoM_S) was 173.25 dB, at an input signal frequency of 97.85 MHz.

Key words: pipeline ADC, SAR ADC, ring amplifier, data register

中图分类号:

TN43

韩守祥, 蒲俊豪, 胡治伟, 张润曦. 基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器设计[J]. 华东师范大学学报（自然科学版）, 2026, 2026(2): 108-116.

Shouxiang HAN, Junhao PU, Zhiwei HU, Runxi ZHANG. High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 108-116.

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参考文献 17

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参考文献	Process/nm	架构	Fs/(MS/s)	BW/MHz	SNDR/dB	Power/mW	FoM_S/dB
[11]	28	V-I-T Pipe	250	125	61.5	3.4	165.2
[12]	7	Pipe SAR&TI DSM	600	300	55.3	13	158.9
[13]	22	Pipe SAR	260	130	60.5	0.97	171.8
[14]	28	Pipe SAR	150	75	67.9	2.3	174.3
[15]	8	Pipe SAR	400	200	62.8	2.08	172.6
[6]	28	TI Pipe SAR	1600	200	71.2	12.5	173.2
[16]	28	TI DSM	1400	70	67	32	160.1
[17]	28	Pipe SAR	350	80	70.1	4.87	172.2
本研究*	55	Pipe SAR	200	100	72.93	9.28	173.25

基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器设计

High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier

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