可编程器件设计中跨时钟域的同步设计问题

华东师范大学学报(自然科学版) ›› 2004, Vol. 2004 ›› Issue (3): 66-70,9.

可编程器件设计中跨时钟域的同步设计问题

雷剑虹，金之诚，沈建国

华东师范大学电子科学技术系，上海 200062

收稿日期:2003-03-18 修回日期:2003-04-14 出版日期:2004-09-25 发布日期:2004-09-25
通讯作者: 雷剑虹

The Timing Problem of Synchronous Design in FPGA/CPLD

LEI Jian-hong， JING Zhi-cheng， SHEN Jian-guo

Department of Electronic Science and Technology, East China Normal University，Shanghai 200062, China

Received:2003-03-18 Revised:2003-04-14 Online:2004-09-25 Published:2004-09-25
Contact: LEI Jian-hong

摘要/Abstract

摘要： 介绍可编程器件异步设计中的亚稳态现象及其可能造成的危害，阐述同步设计的重要性.通过具体的设计实例论证了跨时钟域同步处理的必要性，并给出一种实现跨时钟域同步处理的方法和具体电路实例.

关键词: 亚稳态, 异步设计, 同步设计, Verilog HDL语言, 亚稳态, 异步设计, 同步设计, Verilog HDL语言

Abstract: This paper discusses the timing problem in FPGA/CPLD design. It digs out the reasons of this kind of problem and the influence of them on design. Finally, it concludes with some resolutions for the timing design.

Key words: asynchronous design, synchronous design, verilog HDL, metastablity, asynchronous design, synchronous design, verilog HDL

中图分类号:

TN802

雷剑虹;金之诚;沈建国. 可编程器件设计中跨时钟域的同步设计问题[J]. 华东师范大学学报(自然科学版), 2004, 2004(3): 66-70,9.

LEI Jian-hong;JING Zhi-cheng;SHEN Jian-guo. The Timing Problem of Synchronous Design in FPGA/CPLD[J]. Journal of East China Normal University(Natural Sc, 2004, 2004(3): 66-70,9.