华东师范大学学报(自然科学版) ›› 2026, Vol. 2026 ›› Issue (2): 187-198.doi: 10.3969/j.issn.1000-5641.2026.02.017

• FMCW雷达与信号处理 • 上一篇    

基于FFT降维与亚bin补偿的SAR成像算法及硬件实现

郝英建, 程昱锟, 王敬虔, 黄磊磊*()   

  1. 华东师范大学 微电子电路与系统研究所, 上海 200241
  • 收稿日期:2025-10-31 接受日期:2026-01-10 出版日期:2026-03-25 发布日期:2026-04-03
  • 通讯作者: 黄磊磊 E-mail:llhuang@cee.ecnu.edu.cn
  • 基金资助:
    上海市科委资助项目(22DZ2229004)

SAR imaging algorithm and hardware implementation based on FFT dimensionality reduction and sub-bin compensation

Yingjian HAO, Yukun CHENG, Jingqian WANG, Leilei HUANG*()   

  1. Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai 200241, China
  • Received:2025-10-31 Accepted:2026-01-10 Online:2026-03-25 Published:2026-04-03
  • Contact: Leilei HUANG E-mail:llhuang@cee.ecnu.edu.cn

摘要:

合成孔径雷达在近场高分辨率成像领域具有广泛应用前景, 尤其在自动驾驶、工业无损检测及安防安检等场景中展现出独特优势. 然而, 传统高分辨率合成孔径雷达 (SAR) 成像依赖大点数二维快速傅里叶变换 (FFT) (如1024×1024), 导致计算复杂度高, 内存带宽需求大, 难以在资源受限的嵌入式平台 (如FPGA或SoC) 上实现实时处理. 针对这一挑战, 本文提出了一种低复杂度毫米波SAR成像算法, 并给出了其FPGA实现方案. 该方案首先将前端距离维与方位维FFT点数由1024降至512, 显著降低计算负载; 随后在频域对匹配滤波结果进行中心对齐零填充, 实现无乘法开销的图像上采样; 最后引入三点抛物线距向亚bin补偿技术, 补偿因降维引入的栅格失配误差. 为验证所提方法的有效性, 基于TI的 AWR1843毫米波雷达芯片, 搭建了一套完整的近场SAR数据采集系统, 涵盖雷达控制、机械扫描、数据采集与传输等模块, 并在真实金属目标上开展成像实验. 实验结果表明, 与1024×1024全分辨率基准方法相比, 本文方法在FPGA实现中可将DSP48资源消耗降低55.9%, DDR带宽需求减少50%; 同时在相同像素网格下实现高度一致的视觉效果与结构相似性, 峰值旁瓣比 (PSLR) 退化小于0.25 dB, 结构相似性 (SSIM) 达0.96. 本工作为资源受限平台上的高性能毫米波SAR成像提供了可行的工程解决方案.

关键词: 毫米波SAR, 低复杂度成像, 降维FFT, 频域零填充, 亚bin插值, FPGA实现

Abstract:

Synthetic aperture radar (SAR) has shown significant promise for high-resolution near-field imaging owing to its unique advantages in applications such as autonomous driving, industrial non-destructive testing, and security screening. However, conventional high-resolution SAR imaging relies on large two-dimensional fast Fourier transforms (FFTs) (e.g., 1024×1024), which results in high computational complexity and substantial memory bandwidth requirements that hinder real-time processing on resource-constrained embedded platforms such as field-programmable gate arrays (FPGA) or systems-on-chip (SoC). To address this challenge, we propose a co-optimized low-complexity millimeter-wave SAR imaging scheme based on an algorithm with designated hardware. First, the size of the FFT in both the range and azimuth dimensions is reduced from 1024 to 512, which reduces the computational load significantly. Subsequently, zero-padding with center alignment is applied to the results of matched filtering in the frequency domain to achieve multiplication-free upsampling. Finally, a three-point parabolic sub-bin interpolation technique is introduced to compensate for grid-mismatch errors caused by dimensionality reduction. To validate the effectiveness of the proposed method, a complete near-field SAR data acquisition system based on the TI AWR1843 millimeter-wave radar chip was developed. This system consists of radar control, mechanical scanning, data acquisition, and transmission modules. The imaging experiments were conducted on real metallic targets. The experimental results demonstrate that when implemented on an FPGA, the proposed approach reduces DSP48 resource utilization by 55.9% and cuts the required double data rate (DDR) bandwidth by 50% compared with the baseline full-resolution method using 1024×1024 FFT, while maintaining highly consistent visual quality and structural similarity on the same pixel grid, with the degradation of the peak sidelobe ratio (PSLR) being less than 0.25 dB, and the structural similarity index (SSIM) reaches 0.96. This work provides a practical engineering solution for high-performance millimeter-wave SAR imaging on resource-constrained platforms.

Key words: millimeter-wave SAR, low-complexity imaging, dimensionality-reduced FFT, frequency-domain zero-padding, sub-bin interpolation, FPGA implementation

中图分类号: