Journal of East China Normal University(Natural Sc ›› 2004, Vol. 2004 ›› Issue (3): 66-70,9.

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The Timing Problem of Synchronous Design in FPGA/CPLD

LEI Jian-hong， JING Zhi-cheng， SHEN Jian-guo   

  1. Department of Electronic Science and Technology, East China Normal University，Shanghai 200062, China
  • Received:2003-03-18 Revised:2003-04-14 Online:2004-09-25 Published:2004-09-25
  • Contact: LEI Jian-hong

Abstract: This paper discusses the timing problem in FPGA/CPLD design. It digs out the reasons of this kind of problem and the influence of them on design. Finally, it concludes with some resolutions for the timing design.

Key words: asynchronous design, synchronous design, verilog HDL, metastablity, asynchronous design, synchronous design, verilog HDL

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