High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier

doi:10.3969/j.issn.1000-5641.2026.02.010

Abstract

Abstract:

This study proposes a 12b 200 MS/s pipeline successive approximation analog-to-digital converter (Pipeline SAR ADC) for 5G and Wi-Fi 6E wireless communication applications. To address drawbacks such as slow speed and high power consumption in the residue amplifiers of conventional Pipeline ADC, a pseudo-differential switched-capacitor amplifier based on a self-biased ring amplifier is designed. This design incorporates a reference voltage-halving technique in the second stage to reduce the system power consumption and enhance the overall speed. For traditional gate-bootstrapped switches, optimizations for speed and partial compensation of clock feedthrough effects are implemented. In addition, a set-reset (SR) latched data register is proposed to accelerate the logic circuitry of the SAR ADC. The ADC is designed using a 55 nm CMOS process with a core area of 0.182 mm². The simulation results show that at 27℃ and a 1.2 V supply voltage, the signal-to-noise distortion ratio (SNDR) was 72.93 dB, the power consumption was 9.28 mW, and the Schreier figure of merit (FoM_S) was 173.25 dB, at an input signal frequency of 97.85 MHz.

Key words: pipeline ADC, SAR ADC, ring amplifier, data register

CLC Number:

TN43

Shouxiang HAN, Junhao PU, Zhiwei HU, Runxi ZHANG. High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 108-116.

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Table 1

References 17

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参考文献	Process/nm	架构	Fs/(MS/s)	BW/MHz	SNDR/dB	Power/mW	FoM_S/dB
[11]	28	V-I-T Pipe	250	125	61.5	3.4	165.2
[12]	7	Pipe SAR&TI DSM	600	300	55.3	13	158.9
[13]	22	Pipe SAR	260	130	60.5	0.97	171.8
[14]	28	Pipe SAR	150	75	67.9	2.3	174.3
[15]	8	Pipe SAR	400	200	62.8	2.08	172.6
[6]	28	TI Pipe SAR	1600	200	71.2	12.5	173.2
[16]	28	TI DSM	1400	70	67	32	160.1
[17]	28	Pipe SAR	350	80	70.1	4.87	172.2
本研究*	55	Pipe SAR	200	100	72.93	9.28	173.25