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    25 March 2026, Volume 2026 Issue 2 Previous Issue   
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    RF Front-Ends and Millimeter-Wave Integrated Circuits
    A 28 GHz high power density and high gain Doherty power amplifier
    Yangyang WANG, Leying CAO, Zhe’ao JIANG, Runxi ZHANG
    2026, 2026 (2):  1-11.  doi: 10.3969/j.issn.1000-5641.2026.02.001
    Abstract ( 7 )   HTML ( 4 )   PDF (3062KB) ( 4 )   Save

    This study presents a 28 GHz, high power density, high gain, single-drive four-way Doherty power amplifier (PA) implemented in 40 nm complementary metal-oxide-semiconductor (CMOS) technology. By replacing conventional quadrature splitting networks with a distributed active transformer-based inter-stage quadrature divider, the proposed design achieves reduced insertion loss while significantly enhancing gain and power density. Additionally, a DAT-based single output transformer is introduced to simultaneously realize power combining and load modulation, achieving an optimized high-power-density PA architecture. Measurement results indicate that at 28 GHz, the PA delivers a saturated output power of 22.6 dBm, a 1 dB output compression point of 21.2 dBm, and a power added efficiency (PAE) of 20.5%, with a PAE of 14.2% at 6 dB power back-off. Under a 100 MHz orthogonal frequency-division multiplexing signal modulated with 64-quadrature amplitude modulation, the PA delivers an average output power of 13.5 dBm and an average PAE of 9% while satisfying an error vector magnitude (EVM) requirement of –25 dB. For a 400 MHz signal bandwidth, it maintains an average output power of 11.3 dBm and an average PAE of 8% under the same EVM specification. The core occupies an active area of only 0.38 mm2, corresponding to a power density of 0.48 W/mm2.

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    A high-energy-efficiency and high-linearity digital transmitter based on switched capacitor power amplifier (SCPA) for Wi-Fi communications
    Can LIU, Kangjie ZHAO, Runxi ZHANG
    2026, 2026 (2):  12-24.  doi: 10.3969/j.issn.1000-5641.2026.02.002
    Abstract ( 2 )   HTML ( 2 )   PDF (2314KB) ( 3 )   Save

    This paper presents a 2.4 GHz silicon-based, high output power, high energy efficiency, and high-linearity switched capacitor power amplifier (SCPA) digital transmitter chip designed for Wi-Fi communications. The transmitter comprises two main sections: a digital module and a radio frequency (RF) module. In the RF module, the SCPA adopts a 10 bit resolution in-phase/quadrature (I/Q) architecture. It employs a clock-interleaving technique to eliminate overlap losses during the combination of I/Q signals, thus improving the output power. A cross-coupled four-way series-combining Doherty passive network is utilized to boost output power and power back-off (PBO) efficiency. In the digital module, digital predistortion processing is implemented to optimize the overall linearity of the chip. The chip was designed with a 22 nm complementary metal oxide semiconductor (CMOS) process. Post-simulation results show that the transmitter achieves a saturated output power of 30.44 dBm and a peak system efficiency of 47.73% at 2.4 GHz. At 2.5 dB, 6 dB, and 12 dB PBO, the system efficiencies are 34.73%, 37.92%, and 17.94%, respectively. For a 4096-QAM modulated signal, the final error vector magnitude (EVM) can be achieved to be less than –38 dB.

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    Design of a K-band array antenna with high isolation and broadband gain
    Yang ZHOU, Zhe’ao JIANG, Yue ZHU, Runxi ZHANG
    2026, 2026 (2):  25-34.  doi: 10.3969/j.issn.1000-5641.2026.02.003
    Abstract ( 14 )   HTML ( 3 )   PDF (2504KB) ( 5 )   Save

    Microstrip comb antennas typically adopt parallel microstrip arrangements and are well suited for large-scale array designs because of their fixed element spacing and compact size. However, the bandwidth of comb arrays is often constrained by the resonant characteristics of microstrip lines, and the linear arrangement of elements can easily result in high cross-polarization levels. Microstrip grid array antennas, through symmetric element configurations and coupling design, can achieve flatter gain and broader impedance bandwidth. Furthermore, optimization of the element layout and feed network effectively suppresses sidelobes, improves polarization purity, and reduces transmission loss. This paper proposes a K-band array antenna that integrates a series-fed receiving and a series-parallel-fed transmitting antenna, employing Rogers RO5880 substrate with a dielectric constant of εr=2.2. A Chebyshev amplitude distribution is employed to realize non-uniform excitation of the elements for sidelobe reduction. Measurement results demonstrate that within the 23.0~24.3 GHz band, the antenna achieves an overall gain of 23.4 dBi, with a 3 dB gain bandwidth covering 23.02~24.08 GHz. The inter-array isolation remains below –46 dB across the operating band. At a center frequency of 23.5 GHz, the E-plane and H-plane sidelobe levels are both below –15 dB, indicating suitability for dense applications such as automotive radar, short-range high-data-rate communications, and 5G base stations.

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    A high-power wideband digital Doherty power amplifier for Wi-Fi 6
    Kangjie ZHAO, Can LIU, Runxi ZHANG
    2026, 2026 (2):  35-47.  doi: 10.3969/j.issn.1000-5641.2026.02.004
    Abstract ( 2 )   HTML ( 2 )   PDF (6983KB) ( 2 )   Save

    In this study, we propose a class-G high-power broadband digital Doherty power amplifier (DPA) for Wi-Fi 6 applications, operating from 5.125 to 7.125 GHz. The proposed DPA is based on a polar architecture that combines Doherty load modulation with class-G amplification to achieve optimal efficiency, and it is fabricated using a 22-nm complementary metal-oxide-semiconductor (CMOS) process. At the output, a λ/4 transmission line-integrated transformer-based combining network minimizes insertion loss and enables watt-level output with an 8-bit amplitude modulation module. The results of post-layout simulations showed a saturated output power of 29 dBm, a peak power-added efficiency (PAE) of 23%, and 6- and 12-dB back-off PAEs of 22% and 13%, respectively. For an 80-MHz 256-quadrature amplitude modulation (256-QAM) signal, the DPA delivers an average output power of 21 dBm with an error vector magnitude (EVM) of –30 dB. It also achieves a phase error of less than 6° across a 2-GHz bandwidth via a compact fully differential broadband quadrature input network with an 8-bit phase modulation module. Thus, the proposed DPA meets the wideband, high-efficiency and high-linearity requirements of Wi-Fi 6 systems.

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    A 23.7~35.8 GHz wideband low-noise amplifier for 5G millimeter-wave communication
    Ruohan WANG, Chunqi SHI
    2026, 2026 (2):  48-58.  doi: 10.3969/j.issn.1000-5641.2026.02.005
    Abstract ( 3 )   HTML ( 2 )   PDF (2870KB) ( 4 )   Save

    This paper presents a design of a broadband low-noise amplifier (LNA) for 5G FR2 applications based on a 40 nm CMOS technology. A three-stage differential cascode topology was adopted, incorporating an out-of-phase dual-coupling gm-boosting technique to achieve wide input matching and improved gain. An inductive feedback common-gate shorting technique was employed, resulting in a 5.46 dB improvement in maximum stable gain and a 9.95 dB enhancement in output 1 dB compression point. A hybrid interstage wideband matching network was implemented using a transimpedance peak-flattening and staggering method, achieving a 12 GHz bandwidth. Post-layout simulation results show that the LNA exhibits a peak gain of 13.5 dB, a 3 dB bandwidth from 23.7 to 35.8 GHz, a fractional bandwidth of 41%, a minimum noise figure of 5.74 dB, and an input 1 dB compression point (IP1dB) of –11.8 dBm.

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    A 20~25 GHz transformer-based improved multi-path noise-canceling low noise amplifier
    Ziyao WANG, Yuri LU, Runxi ZHANG
    2026, 2026 (2):  59-70.  doi: 10.3969/j.issn.1000-5641.2026.02.006
    Abstract ( 3 )   HTML ( 2 )   PDF (1934KB) ( 1 )   Save

    This paper presents a 20~25 GHz low noise amplifier that employs a transformer-based improved multi-path noise-canceling (IMNC) architecture. The proposed IMNC approach addresses key limitations of the conventional dual-path noise-canceling (DPNC) technique that employs common-source (CS) and common-gate (CG) stages to suppress each other's noise. In DPNC designs, noise from the CG stage cannot be fully canceled, and increasing CG transconductance to enhance CS-stage noise suppression results in a tradeoff between noise performance and power consumption. To overcome these limitations, the proposed IMNC architecture introduces a three-coil transformer that passively boosts the gain of the CG stage, thereby improving CS-stage noise cancellation without additional power consumption. The transformer also provides an additional noise-canceling path that enables partial self-cancellation of CG stage noise. These improvements lead to better noise performance and power efficiency compared to the conventional DPNC approach. Fabricated in a 40 nm complementary metal oxide semiconductor (CMOS) process, the proposed low noise amplifier achieves a peak gain of 14.5 dB, a 3 dB bandwidth of 5.1 GHz spanning 20 to 25 GHz, and a minimum noise figure (NF) of 2.0 dB, while consuming 22.4 mW of power and occupying a core area of 0.16 mm2.

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    A 70.3~86.6 GHz broadband low-noise amplifier utilizing source-gate-coupled-transformer technique
    Leying CAO, Yangyang WANG, Yuxin SHU, Runxi ZHANG
    2026, 2026 (2):  71-81.  doi: 10.3969/j.issn.1000-5641.2026.02.007
    Abstract ( 4 )   HTML ( 2 )   PDF (1602KB) ( 3 )   Save

    A 70.3~86.6 GHz low-noise amplifier (LNA) was investigated, which can be applied simultaneously to E-band communication and 77 GHz automotive radar systems. The LNA employs a three-stage differential architecture to suppress common-mode noise. In the input stage, a source-gate-coupled-transformer-based noise-cancellation and equivalent transconductance enhancement technique is implemented to simultaneously reduce noise and boost gain. Together with a single-ended-to-differential balun, the input network achieves both impedance and optimal noise matching. The intermediate stage uses a common-source configuration with neutralization capacitors to improve gain and stability, while the output stage employs a cascode topology with a common-gate short-circuit technique and dual neutralization capacitors scheme to mitigate parasitic effects and further enhance gain and stability. Additionally, an inductor is introduced between the source of the common-gate transistor and the drain of the common-source transistor to alleviate parasitic effects and extend the cutoff frequency. Simulation results demonstrate that the proposed LNA achieves a peak gain of 22.54 dB, a 3 dB bandwidth covering 70.3~86.6 GHz, and a minimum noise figure of 5.48 dB, with noise variation less than 0.69 dB across the operating band. The input and output return losses are both better than those at –8.5 dB, and the input 1 dB compression point (IP1dB) is –16.39 dBm.

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    Power Management and Data Converters
    High-efficiency, tri-mode, low-EMI synchronized buck DC-DC converter
    Shixiang DING, Songmao HAO, Chunqi SHI
    2026, 2026 (2):  82-94.  doi: 10.3969/j.issn.1000-5641.2026.02.008
    Abstract ( 5 )   HTML ( 2 )   PDF (3477KB) ( 2 )   Save

    This paper presents a tri-mode buck converter designed using the 55 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, which offers a peak efficiency of 92.95% for low-EMI applications. The converter employs a seamless transition between pulse-width modulation (PWM), pulse-frequency modulation (PFM), and pulse-skip modulation (PSM) modes under various load conditions, which optimizes the efficiency and ripple performance from light to heavy loads. By implementing spread-spectrum frequency modulation with 35% frequency dithering, the converter reduces the peak of the output voltage spectrum by 22 dB, thus significantly reducing the EMI emission spectrum.

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    A wide-range high-efficiency peak-current-mode Buck DC-DC converter based on adaptive quadratic slope compensation
    Xuyang LI, Xiaodi ZHOU, Yanwen WU, Songmao HAO, Chunqi SHI
    2026, 2026 (2):  95-107.  doi: 10.3969/j.issn.1000-5641.2026.02.009
    Abstract ( 3 )   HTML ( 2 )   PDF (1885KB) ( 2 )   Save

    This paper presents a high-efficiency peak current-mode (PCM) Buck DC-DC converter utilizing adaptive quadratic slope compensation. The proposed design generates tailored adaptive slope voltages across wide ranges of input voltage, output voltage, load current, and switching frequency, resulting in excellent transient performance. Fabricated in a 55 nm BCD process, the chip occupies a compact core area of only 0.186 mm2. It supports an input voltage range of 3.7~5.0 V, an output voltage range of 1.5~3.5 V, a maximum load current of 1.00 A, and a switching frequency configurable from 1.0 MHz to 4.0 MHz. The converter achieves a peak efficiency of 96.0%, maintains efficiency above 93.0% at 1.00 A output current, and delivers over 90.0% efficiency across the load range from 0.03 A to 1.00 A. Post-layout simulation results confirm that the proposed compensation technique exhibits strong adaptability under varied application configurations.

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    High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier
    Shouxiang HAN, Junhao PU, Zhiwei HU, Runxi ZHANG
    2026, 2026 (2):  108-116.  doi: 10.3969/j.issn.1000-5641.2026.02.010
    Abstract ( 3 )   HTML ( 2 )   PDF (2194KB) ( 3 )   Save

    This study proposes a 12b 200 MS/s pipeline successive approximation analog-to-digital converter (Pipeline SAR ADC) for 5G and Wi-Fi 6E wireless communication applications. To address drawbacks such as slow speed and high power consumption in the residue amplifiers of conventional Pipeline ADC, a pseudo-differential switched-capacitor amplifier based on a self-biased ring amplifier is designed. This design incorporates a reference voltage-halving technique in the second stage to reduce the system power consumption and enhance the overall speed. For traditional gate-bootstrapped switches, optimizations for speed and partial compensation of clock feedthrough effects are implemented. In addition, a set-reset (SR) latched data register is proposed to accelerate the logic circuitry of the SAR ADC. The ADC is designed using a 55 nm CMOS process with a core area of 0.182 mm2. The simulation results show that at 27℃ and a 1.2 V supply voltage, the signal-to-noise distortion ratio (SNDR) was 72.93 dB, the power consumption was 9.28 mW, and the Schreier figure of merit (FoMS) was 173.25 dB, at an input signal frequency of 97.85 MHz.

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    Design of a high-precision third-order NS SAR ADC for audio applications
    Nannan GENG, Jikun WANG, Shouxiang HAN, Chunqi SHI
    2026, 2026 (2):  117-127.  doi: 10.3969/j.issn.1000-5641.2026.02.011
    Abstract ( 1 )   HTML ( 2 )   PDF (1420KB) ( 1 )   Save

    This paper proposes the design of a high-precision third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) for audio applications. The NS effect of passive NS circuits deteriorates owing to gain loss. In response, a cascaded integral feed-forward (CIFF) active NS loop is designed. To mitigate the impact of integrator nonlinearity on the ADC, a primary-auxiliary dual-path high-linearity source follower structure is proposed. This source follower buffers the residual voltage onto the integration capacitor, ultimately achieving third-order NS performance. A mismatch error shaping (MES) technique is incorporated to mitigate nonlinearities induced by digital-to-analog converter (DAC) mismatches. Fabricated in a 55 nm CMOS process, the ADC core occupies approximately 0.25 mm2. Post-layout simulation results demonstrate that under a 1.8 V supply voltage at 40℃, while operating at a sampling frequency of 8 MS/s with a bandwidth of 125 kHz and consuming 10.83 mW of power, the ADC achieves an effective number of bits (ENOB) of 15.14 and a signal-to-noise and distortion ratio (SNDR) of 92.92 dB with a Schreier figure of merit (FoMS) of 163.54 dB.

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    FMCW Radar and Signal Processing
    A fully-integrated Doppler-assisted FMCW radar for indoor localization and vital sign sensing
    Yuqin ZHANG, Zitong ZHANG, Runxi ZHANG
    2026, 2026 (2):  128-138.  doi: 10.3969/j.issn.1000-5641.2026.02.012
    Abstract ( 2 )   HTML ( 2 )   PDF (2133KB) ( 1 )   Save

    This paper presents a Doppler-assisted frequency-modulated continuous-wave (FMCW) radar that combines the precise range resolution capability of FMCW with the high sensitivity of Doppler radar, enabling versatile performance for indoor applications. A comprehensive analysis of low-frequency noise contributions from key receiver blocks, including the low-noise amplifier (LNA), mixer, local oscillator (LO) buffer, and analog baseband (ABB) circuits, is conducted. An “RF+LO+BB” joint noise figure (NF) improvement method is proposed to effectively suppress the low-frequency noise. To reduce frequency modulation (FM) error in charge-pump-based fractional-N phase-locked loop (PLL), a nested-PLL architecture with a co-optimized loop parameter selection method is employed, resulting in significantly improved chirp linearity. Fabricated in a 55 nm CMOS technology, the proposed Doppler-assisted FMCW radar achieves NFs of 32 dB and 12 dB at 10 Hz and 1 kHz, respectively, and a chirp linearity of 0.0039% over a 3.52 GHz chirp bandwidth (BW), resulting in a maximum detection range of 19.41 m and a range resolution of 4.7 cm. The radar occupies a die area of 12.7 mm2 and consumes 594 mW in FMCW mode and 432 mW in Doppler mode under a 3.3 V supply.

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    Analog-baseband circuit with large dynamic range and fine-grained gain control for 77-GHz millimeter-wave radar systems
    Zihao REN, Cong ZHANG, Yang YANG, Chunqi SHI
    2026, 2026 (2):  139-150.  doi: 10.3969/j.issn.1000-5641.2026.02.013
    Abstract ( 4 )   HTML ( 2 )   PDF (2186KB) ( 1 )   Save

    In this study, an analog-baseband (ABB) circuit for 77 GHz automotive radar transceivers, which features a large dynamic range and fine-grained gain control, is proposed and implemented. To accommodate various detection ranges from short (15 m) to long distance (250 m), the circuit employs a Butterworth filter supporting a signal bandwidth of 400 kHz to 20 MHz with a continuously tunable gain of 10 to 57 dB. A precision gain control strategy is proposed, which enables 2.5 dB/step gain adjustments to precisely maintain the output amplitude within 460–740 mV. A feedback-based direct current (DC) offset cancellation loop effectively suppresses residual DC offsets. The hybrid digital-analog feedback automatic gain control ensures a settling time of less than 160 μs during rapid signal amplitude variations. At the output stage, a highly linear source-follower structure is implemented to minimize signal distortion while enhancing the ABB’s driving capability. Measured results indicate that under a 2.5 V power supply, the analog baseband affords a wide range of automatic gain tuning from 10 to 57 dB across the full operating bandwidth (400 kHz–20 MHz). At the maximum gain, the circuit exhibits noise figures of 42.4 and 33.1 dB at 400 kHz and 20 MHz, respectively.

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    Lanczos compression-based FMCW radar target detection scheme
    Ying LIU, Beibei XING, Zhixin YIN, Leilei HUANG, Chunqi SHI
    2026, 2026 (2):  151-163.  doi: 10.3969/j.issn.1000-5641.2026.02.014
    Abstract ( 1 )   HTML ( 2 )   PDF (1754KB) ( 1 )   Save

    Frequency Modulated Continuous-Wave (FMCW) radar has been widely adopted in fields such as autonomous driving and security surveillance due to its high resolution, strong penetration capability, and low power consumption. However, traditional target detection methods based on two-dimensional Fast Fourier Transform (2D-FFT) suffer from high computational complexity and significant latency when processing large-scale intermediate frequency (IF) data, making it challenging to meet millisecond-level real-time requirements. To address these issues, this paper proposes a Lanczos compression-based accelerated Constant False Alarm Rate (CFAR) detection method deployed on an FPGA platform. By employing Krylov subspace projection to approximate principal component vectors, the computational complexity is reduced from O(NMlog(NM)) to O(NM). The algorithm first applies one-dimensional CFAR after principal component projection to obtain candidate points, followed by a refined two-dimensional CFAR window for target confirmation, effectively reducing computational load while maintaining detection accuracy. Experimental results on the Xilinx XC7Z020CLG400 FPGA platform demonstrate that the proposed scheme achieves a latency of only 0.36 ms when processing a 256×512 matrix, with an average power consumption of 0.76 W. In both public datasets and simulated multi-target scenarios, the system achieved an average false alarm rate of 0.48% and a miss rate of 2.93%, validating the high precision, low latency, and energy efficiency of the proposed method. This research provides a high-performance, low-power hardware solution for real-time target detection in millimeter-wave radar applications, with broad prospects for engineering applications.

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    Data-compression method for full-dimension data in FMCW radar systems and its hardware implementation
    Zhixin YIN, Ying LIU, Beibei XING, Leilei HUANG, Runxi ZHANG
    2026, 2026 (2):  164-175.  doi: 10.3969/j.issn.1000-5641.2026.02.015
    Abstract ( 1 )   HTML ( 2 )   PDF (1565KB) ( 1 )   Save

    This study proposes a full-dimension data-compression method and its corresponding hardware-implementation scheme for frequency-modulated continuous wave (FMCW) radar processing systems. In accommodating the continuously increasing demand for higher measurement accuracies and resolutions in FMCW radar, the processing system generates a rapidly increasing data volume, thus placing a significant burden on the data-transmission bandwidth and storage resources. Hence, a compression algorithm based on k-th-order exponential Golomb encoding (EGE) is introduced. The algorithm first performs data pre-compression using exponential Golomb encoding to reduce statistical redundancy and then optimizes the compressed output through adaptive significant-bit truncation, thus achieving efficient bit-width alignment. Suitable for full-dimension data formats in FMCW radar systems, the method demonstrates strong adaptability, high compression efficiency, and the ability to support real-time data processing with a hardware-friendly architecture. Experimental results indicate that the proposed algorithm reduces storage consumption by more than 50% while preserving data quality, thus significantly enhancing both processing efficiency and data-transmission capacity while demonstrating significant potential for practical engineering applications.

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    A high-speed adaptive γ filtering hardware implementation scheme for back projection imaging
    Yukun CHENG, Yingjian HAO, Jingqian WANG, Leilei HUANG
    2026, 2026 (2):  176-186.  doi: 10.3969/j.issn.1000-5641.2026.02.016
    Abstract ( 1 )   HTML ( 2 )   PDF (1714KB) ( 1 )   Save

    With the increasing complexity of public security, indoor security inspection demands higher imaging precision and real-time performance. Traditional X-ray and millimeter-wave imaging systems exhibit limitations in safety, resolution, and anti-interference capability. Near-field synthetic aperture radar, with its high resolution and non-contact advantages, has emerged as a promising alternative. However, although the back projection algorithm achieves precise focusing, speckle noise significantly degrades image quality, limiting its practical application. To address this issue, this paper proposes and implements a fast filtering strategy and hardware-oriented solution for back projection imaging. At the algorithm level, local statistics are rapidly computed using integral images, combined with adaptive γ modeling to achieve efficient speckle suppression while preserving edge details. At the hardware level, image blocking, multi-unit parallel reuse, and pipelined architecture are employed to accelerate filtering and reduce latency, while neighborhood extension is used to mitigate edge distortion caused by blocking. Experimental results demonstrate that, for a 300×300 synthetic aperture data, the filtering time is reduced to approximately 6.67 ms, equivalent number of looks increases from 5.19 to 11.47, edge structure deviation decreases from 0.19 to 0.13, and peak signal-to-noise ratio reaches 39.27 dB, significantly outperforming traditional Lee or Kuan filters. Hardware implementation results indicate that the proposed architecture achieves advantages in resource utilization and real-time performance, confirming its practicality in efficient and scalable indoor synthetic aperture radar image filtering and providing reliable technical support for next-generation indoor security inspection systems.

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    SAR imaging algorithm and hardware implementation based on FFT dimensionality reduction and sub-bin compensation
    Yingjian HAO, Yukun CHENG, Jingqian WANG, Leilei HUANG
    2026, 2026 (2):  187-198.  doi: 10.3969/j.issn.1000-5641.2026.02.017
    Abstract ( 1 )   HTML ( 2 )   PDF (1747KB) ( 1 )   Save

    Synthetic aperture radar (SAR) has shown significant promise for high-resolution near-field imaging owing to its unique advantages in applications such as autonomous driving, industrial non-destructive testing, and security screening. However, conventional high-resolution SAR imaging relies on large two-dimensional fast Fourier transforms (FFTs) (e.g., 1024×1024), which results in high computational complexity and substantial memory bandwidth requirements that hinder real-time processing on resource-constrained embedded platforms such as field-programmable gate arrays (FPGA) or systems-on-chip (SoC). To address this challenge, we propose a co-optimized low-complexity millimeter-wave SAR imaging scheme based on an algorithm with designated hardware. First, the size of the FFT in both the range and azimuth dimensions is reduced from 1024 to 512, which reduces the computational load significantly. Subsequently, zero-padding with center alignment is applied to the results of matched filtering in the frequency domain to achieve multiplication-free upsampling. Finally, a three-point parabolic sub-bin interpolation technique is introduced to compensate for grid-mismatch errors caused by dimensionality reduction. To validate the effectiveness of the proposed method, a complete near-field SAR data acquisition system based on the TI AWR1843 millimeter-wave radar chip was developed. This system consists of radar control, mechanical scanning, data acquisition, and transmission modules. The imaging experiments were conducted on real metallic targets. The experimental results demonstrate that when implemented on an FPGA, the proposed approach reduces DSP48 resource utilization by 55.9% and cuts the required double data rate (DDR) bandwidth by 50% compared with the baseline full-resolution method using 1024×1024 FFT, while maintaining highly consistent visual quality and structural similarity on the same pixel grid, with the degradation of the peak sidelobe ratio (PSLR) being less than 0.25 dB, and the structural similarity index (SSIM) reaches 0.96. This work provides a practical engineering solution for high-performance millimeter-wave SAR imaging on resource-constrained platforms.

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    Cross-layer design and multi-scenario optimization methods for CMOS high-energy-efficiency edge computing chips
    Xu WANG, Ke CHEN, Chenghua WANG, Weiqiang LIU
    2026, 2026 (2):  199-213.  doi: 10.3969/j.issn.1000-5641.2026.02.018
    Abstract ( 1 )   HTML ( 2 )   PDF (1178KB) ( 1 )   Save

    As integrated circuit technologies progressively enter the post-Moore era, performance and energy-efficiency improvements achieved solely through transistor scaling have become increasingly difficult to sustain. Energy efficiency has thus emerged as a critical factor limiting further performance scaling and application deployment. In particular, for emerging application scenarios represented by edge computing, chip design is subject to more stringent and diverse constraints due to tight power budgets, area costs, and real-time requirements. Under these conditions, the optimization focus of advanced Complementary Metal-Oxide-Semiconductor (CMOS) chip design is shifting from process-centric scaling toward a design-driven paradigm that emphasizes cross-layer coordinated optimization across the circuit, architecture, and system levels. This paper presents a systematic and application-oriented review of key techniques and methodological frameworks for CMOS high-energy-efficiency chip design targeting edge computing. First, from the perspective of the post-Moore technological context, the intrinsic causes of energy-efficiency bottlenecks and their manifestations under low-power constraints are analyzed. Subsequently, following a cross-layer organizational hierarchy spanning the circuit level, the architectural level, and emerging computing paradigms, representative design methodologies enabling high-energy-efficiency edge computing are comprehensively reviewed, with emphasis on their underlying energy-efficiency mechanisms and design trade-offs. Building on this foundation, multiple representative edge application scenarios—including artificial intelligence inference, edge intelligence and the Internet of Things, as well as communication and signal processing—are examined to elucidate how application-specific constraints give rise to distinct energy-efficiency bottlenecks and corresponding optimization strategies. Finally, the major challenges facing CMOS high-energy-efficiency chip design for edge computing are summarized, and future research trends are discussed, with the aim of providing cross-layer design insights and systematic methodological references for high-energy-efficiency edge computing chip design under complex post-Moore application constraints.

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