Abstract:

As integrated circuit technologies progressively enter the post-Moore era, performance and energy-efficiency improvements achieved solely through transistor scaling have become increasingly difficult to sustain. Energy efficiency has thus emerged as a critical factor limiting further performance scaling and application deployment. In particular, for emerging application scenarios represented by edge computing, chip design is subject to more stringent and diverse constraints due to tight power budgets, area costs, and real-time requirements. Under these conditions, the optimization focus of advanced Complementary Metal-Oxide-Semiconductor (CMOS) chip design is shifting from process-centric scaling toward a design-driven paradigm that emphasizes cross-layer coordinated optimization across the circuit, architecture, and system levels. This paper presents a systematic and application-oriented review of key techniques and methodological frameworks for CMOS high-energy-efficiency chip design targeting edge computing. First, from the perspective of the post-Moore technological context, the intrinsic causes of energy-efficiency bottlenecks and their manifestations under low-power constraints are analyzed. Subsequently, following a cross-layer organizational hierarchy spanning the circuit level, the architectural level, and emerging computing paradigms, representative design methodologies enabling high-energy-efficiency edge computing are comprehensively reviewed, with emphasis on their underlying energy-efficiency mechanisms and design trade-offs. Building on this foundation, multiple representative edge application scenarios—including artificial intelligence inference, edge intelligence and the Internet of Things, as well as communication and signal processing—are examined to elucidate how application-specific constraints give rise to distinct energy-efficiency bottlenecks and corresponding optimization strategies. Finally, the major challenges facing CMOS high-energy-efficiency chip design for edge computing are summarized, and future research trends are discussed, with the aim of providing cross-layer design insights and systematic methodological references for high-energy-efficiency edge computing chip design under complex post-Moore application constraints.

Key words: CMOS high-energy-efficiency chips, edge computing, energy-efficiency optimization, design-driven methodology, architectural optimization, emerging computing paradigms