J* E* C* N* U* N* S* ›› 2026, Vol. 2026 ›› Issue (2): 187-198.doi: 10.3969/j.issn.1000-5641.2026.02.017

• FMCW Radar and Signal Processing • Previous Articles    

SAR imaging algorithm and hardware implementation based on FFT dimensionality reduction and sub-bin compensation

Yingjian HAO, Yukun CHENG, Jingqian WANG, Leilei HUANG*()   

  1. Institute of Microelectronic Circuits and Systems, East China Normal University, Shanghai 200241, China
  • Received:2025-10-31 Accepted:2026-01-10 Online:2026-03-25 Published:2026-04-03
  • Contact: Leilei HUANG E-mail:llhuang@cee.ecnu.edu.cn

Abstract:

Synthetic aperture radar (SAR) has shown significant promise for high-resolution near-field imaging owing to its unique advantages in applications such as autonomous driving, industrial non-destructive testing, and security screening. However, conventional high-resolution SAR imaging relies on large two-dimensional fast Fourier transforms (FFTs) (e.g., 1024×1024), which results in high computational complexity and substantial memory bandwidth requirements that hinder real-time processing on resource-constrained embedded platforms such as field-programmable gate arrays (FPGA) or systems-on-chip (SoC). To address this challenge, we propose a co-optimized low-complexity millimeter-wave SAR imaging scheme based on an algorithm with designated hardware. First, the size of the FFT in both the range and azimuth dimensions is reduced from 1024 to 512, which reduces the computational load significantly. Subsequently, zero-padding with center alignment is applied to the results of matched filtering in the frequency domain to achieve multiplication-free upsampling. Finally, a three-point parabolic sub-bin interpolation technique is introduced to compensate for grid-mismatch errors caused by dimensionality reduction. To validate the effectiveness of the proposed method, a complete near-field SAR data acquisition system based on the TI AWR1843 millimeter-wave radar chip was developed. This system consists of radar control, mechanical scanning, data acquisition, and transmission modules. The imaging experiments were conducted on real metallic targets. The experimental results demonstrate that when implemented on an FPGA, the proposed approach reduces DSP48 resource utilization by 55.9% and cuts the required double data rate (DDR) bandwidth by 50% compared with the baseline full-resolution method using 1024×1024 FFT, while maintaining highly consistent visual quality and structural similarity on the same pixel grid, with the degradation of the peak sidelobe ratio (PSLR) being less than 0.25 dB, and the structural similarity index (SSIM) reaches 0.96. This work provides a practical engineering solution for high-performance millimeter-wave SAR imaging on resource-constrained platforms.

Key words: millimeter-wave SAR, low-complexity imaging, dimensionality-reduced FFT, frequency-domain zero-padding, sub-bin interpolation, FPGA implementation

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