Abstract:

This paper presents a 2.4 GHz silicon-based, high output power, high energy efficiency, and high-linearity switched capacitor power amplifier (SCPA) digital transmitter chip designed for Wi-Fi communications. The transmitter comprises two main sections: a digital module and a radio frequency (RF) module. In the RF module, the SCPA adopts a 10 bit resolution in-phase/quadrature (I/Q) architecture. It employs a clock-interleaving technique to eliminate overlap losses during the combination of I/Q signals, thus improving the output power. A cross-coupled four-way series-combining Doherty passive network is utilized to boost output power and power back-off (PBO) efficiency. In the digital module, digital predistortion processing is implemented to optimize the overall linearity of the chip. The chip was designed with a 22 nm complementary metal oxide semiconductor (CMOS) process. Post-simulation results show that the transmitter achieves a saturated output power of 30.44 dBm and a peak system efficiency of 47.73% at 2.4 GHz. At 2.5 dB, 6 dB, and 12 dB PBO, the system efficiencies are 34.73%, 37.92%, and 17.94%, respectively. For a 4096-QAM modulated signal, the final error vector magnitude (EVM) can be achieved to be less than –38 dB.

Key words: complementary metal oxide semiconductor (CMOS), switched capacitor power amplifier (SCPA), in-phase/quadrature (I/Q) architecture digital transmitter, Doherty series-combining transformer, Wi-Fi communications