Data-compression method for full-dimension data in FMCW radar systems and its hardware implementation

doi:10.3969/j.issn.1000-5641.2026.02.015

Abstract

Abstract:

This study proposes a full-dimension data-compression method and its corresponding hardware-implementation scheme for frequency-modulated continuous wave (FMCW) radar processing systems. In accommodating the continuously increasing demand for higher measurement accuracies and resolutions in FMCW radar, the processing system generates a rapidly increasing data volume, thus placing a significant burden on the data-transmission bandwidth and storage resources. Hence, a compression algorithm based on k-th-order exponential Golomb encoding (EGE) is introduced. The algorithm first performs data pre-compression using exponential Golomb encoding to reduce statistical redundancy and then optimizes the compressed output through adaptive significant-bit truncation, thus achieving efficient bit-width alignment. Suitable for full-dimension data formats in FMCW radar systems, the method demonstrates strong adaptability, high compression efficiency, and the ability to support real-time data processing with a hardware-friendly architecture. Experimental results indicate that the proposed algorithm reduces storage consumption by more than 50% while preserving data quality, thus significantly enhancing both processing efficiency and data-transmission capacity while demonstrating significant potential for practical engineering applications.

Key words: frequency-modulated continuous wave (FMCW) radar, exponential Golomb encoding (EGE), data compression, hardware implementation

CLC Number:

TN432

Zhixin YIN, Ying LIU, Beibei XING, Leilei HUANG, Runxi ZHANG. Data-compression method for full-dimension data in FMCW radar systems and its hardware implementation[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 164-175.

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面积		功耗
面积类型	面积/μm²	功耗类型	功耗值/mW
组合逻辑面积	22.669	内部功耗	1.69
Buf 面积	2.587	开关功耗	5.02×10^–3
时序逻辑面积	7.608	泄漏功耗	1.35×10^–3
总面积	31.277	总功耗	1.71

算法类型	数据压缩维度			数据典型压缩率/%			算法是否实时	是否硬件实现
算法类型	ADC	1D-FFT	2D-FFT	ADC	1D-FFT	2D-FFT	算法是否实时	是否硬件实现
本文	√	√	√	45	30	30	√	√
文献[3]	√	×	×	43	–	–	×	×
文献[4]	√	×	×	44	–	–	×	×
文献[5]	×	√	×	–	25		√	√
文献[6]	×	√	√	–	16.7	16.7	√	×
文献[7]	×	×	√	–	–	14	√	√
文献[8]	√	×	×	25	–	–	×	×

硬件实现方式	工艺节点	时钟频率	面积/μm²	功耗/mW
本文	55 nm CMOS	200 MHz	31.277	1.71
文献[5]	45 nm CMOS	300 MHz	–	全芯片2250
文献[7]	55 nm CMOS	500 MHz	18.090	1.14
文献[13]	40 nm CMOS	14.4 kHz	1.806	0.376
文献[14]	0.18 μm CMOS	100 MHz	45.987	3.64