A 23.7~35.8 GHz wideband low-noise amplifier for 5G millimeter-wave communication

doi:10.3969/j.issn.1000-5641.2026.02.005

Abstract

Abstract:

This paper presents a design of a broadband low-noise amplifier (LNA) for 5G FR2 applications based on a 40 nm CMOS technology. A three-stage differential cascode topology was adopted, incorporating an out-of-phase dual-coupling gm-boosting technique to achieve wide input matching and improved gain. An inductive feedback common-gate shorting technique was employed, resulting in a 5.46 dB improvement in maximum stable gain and a 9.95 dB enhancement in output 1 dB compression point. A hybrid interstage wideband matching network was implemented using a transimpedance peak-flattening and staggering method, achieving a 12 GHz bandwidth. Post-layout simulation results show that the LNA exhibits a peak gain of 13.5 dB, a 3 dB bandwidth from 23.7 to 35.8 GHz, a fractional bandwidth of 41%, a minimum noise figure of 5.74 dB, and an input 1 dB compression point (IP1dB) of –11.8 dBm.

Key words: low-noise amplifier (LNA), millimeter-wave (mm-wave), wideband, out-of-phase dual-coupling gm-boosting technique, inductive feedback common-gate-shorting technique

CLC Number:

TN432

Ruohan WANG, Chunqi SHI. A 23.7~35.8 GHz wideband low-noise amplifier for 5G millimeter-wave communication[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 48-58.

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Table 1

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数据来源	工艺	3 dB带宽/GHz	增益/dB	噪声系数/dB	IP1dB/dBm	功耗/mW	面积/mm²	FOM
本研究	40 nm CMOS	12.0(23.7~35.8)	13.50	5.74	–11.8	75.00	0.42	48.65
IMS’2020^[6]	28 nm CMOS	3.4(22.4~25.8)	29.90	5.63	–40.0	25.60	0.22	11.23
IEICE’2018^[13]	180 nm CMOS	4.0	19.80	4.70	–12.0	48.00	0.80	38.90
RFIC’2019^[14]	65 nm CMOS	7.6(24.9~32.5)	18.33	3.25~4.20	–24.0	20.50	0.11	73.37
MWCL’2022^[15]	28 nm CMOS	6.6(69.6~76.2)	13.48	4.56	–16.3	3.64	0.28	54.48