This study presents a 28 GHz, high power density, high gain, single-drive four-way Doherty power amplifier (PA) implemented in 40 nm complementary metal-oxide-semiconductor (CMOS) technology. By replacing conventional quadrature splitting networks with a distributed active transformer-based inter-stage quadrature divider, the proposed design achieves reduced insertion loss while significantly enhancing gain and power density. Additionally, a DAT-based single output transformer is introduced to simultaneously realize power combining and load modulation, achieving an optimized high-power-density PA architecture. Measurement results indicate that at 28 GHz, the PA delivers a saturated output power of 22.6 dBm, a 1 dB output compression point of 21.2 dBm, and a power added efficiency (PAE) of 20.5%, with a PAE of 14.2% at 6 dB power back-off. Under a 100 MHz orthogonal frequency-division multiplexing signal modulated with 64-quadrature amplitude modulation, the PA delivers an average output power of 13.5 dBm and an average PAE of 9% while satisfying an error vector magnitude (EVM) requirement of –25 dB. For a 400 MHz signal bandwidth, it maintains an average output power of 11.3 dBm and an average PAE of 8% under the same EVM specification. The core occupies an active area of only 0.38 mm2, corresponding to a power density of 0.48 W/mm2.
This paper presents a 2.4 GHz silicon-based, high output power, high energy efficiency, and high-linearity switched capacitor power amplifier (SCPA) digital transmitter chip designed for Wi-Fi communications. The transmitter comprises two main sections: a digital module and a radio frequency (RF) module. In the RF module, the SCPA adopts a 10 bit resolution in-phase/quadrature (I/Q) architecture. It employs a clock-interleaving technique to eliminate overlap losses during the combination of I/Q signals, thus improving the output power. A cross-coupled four-way series-combining Doherty passive network is utilized to boost output power and power back-off (PBO) efficiency. In the digital module, digital predistortion processing is implemented to optimize the overall linearity of the chip. The chip was designed with a 22 nm complementary metal oxide semiconductor (CMOS) process. Post-simulation results show that the transmitter achieves a saturated output power of 30.44 dBm and a peak system efficiency of 47.73% at 2.4 GHz. At 2.5 dB, 6 dB, and 12 dB PBO, the system efficiencies are 34.73%, 37.92%, and 17.94%, respectively. For a 4096-QAM modulated signal, the final error vector magnitude (EVM) can be achieved to be less than –38 dB.
Microstrip comb antennas typically adopt parallel microstrip arrangements and are well suited for large-scale array designs because of their fixed element spacing and compact size. However, the bandwidth of comb arrays is often constrained by the resonant characteristics of microstrip lines, and the linear arrangement of elements can easily result in high cross-polarization levels. Microstrip grid array antennas, through symmetric element configurations and coupling design, can achieve flatter gain and broader impedance bandwidth. Furthermore, optimization of the element layout and feed network effectively suppresses sidelobes, improves polarization purity, and reduces transmission loss. This paper proposes a K-band array antenna that integrates a series-fed receiving and a series-parallel-fed transmitting antenna, employing Rogers RO5880 substrate with a dielectric constant of εr=2.2. A Chebyshev amplitude distribution is employed to realize non-uniform excitation of the elements for sidelobe reduction. Measurement results demonstrate that within the 23.0~24.3 GHz band, the antenna achieves an overall gain of 23.4 dBi, with a 3 dB gain bandwidth covering 23.02~24.08 GHz. The inter-array isolation remains below –46 dB across the operating band. At a center frequency of 23.5 GHz, the E-plane and H-plane sidelobe levels are both below –15 dB, indicating suitability for dense applications such as automotive radar, short-range high-data-rate communications, and 5G base stations.
In this study, we propose a class-G high-power broadband digital Doherty power amplifier (DPA) for Wi-Fi 6 applications, operating from 5.125 to 7.125 GHz. The proposed DPA is based on a polar architecture that combines Doherty load modulation with class-G amplification to achieve optimal efficiency, and it is fabricated using a 22-nm complementary metal-oxide-semiconductor (CMOS) process. At the output, a λ/4 transmission line-integrated transformer-based combining network minimizes insertion loss and enables watt-level output with an 8-bit amplitude modulation module. The results of post-layout simulations showed a saturated output power of 29 dBm, a peak power-added efficiency (PAE) of 23%, and 6- and 12-dB back-off PAEs of 22% and 13%, respectively. For an 80-MHz 256-quadrature amplitude modulation (256-QAM) signal, the DPA delivers an average output power of 21 dBm with an error vector magnitude (EVM) of –30 dB. It also achieves a phase error of less than 6° across a 2-GHz bandwidth via a compact fully differential broadband quadrature input network with an 8-bit phase modulation module. Thus, the proposed DPA meets the wideband, high-efficiency and high-linearity requirements of Wi-Fi 6 systems.
This paper presents a design of a broadband low-noise amplifier (LNA) for 5G FR2 applications based on a 40 nm CMOS technology. A three-stage differential cascode topology was adopted, incorporating an out-of-phase dual-coupling gm-boosting technique to achieve wide input matching and improved gain. An inductive feedback common-gate shorting technique was employed, resulting in a 5.46 dB improvement in maximum stable gain and a 9.95 dB enhancement in output 1 dB compression point. A hybrid interstage wideband matching network was implemented using a transimpedance peak-flattening and staggering method, achieving a 12 GHz bandwidth. Post-layout simulation results show that the LNA exhibits a peak gain of 13.5 dB, a 3 dB bandwidth from 23.7 to 35.8 GHz, a fractional bandwidth of 41%, a minimum noise figure of 5.74 dB, and an input 1 dB compression point (IP1dB) of –11.8 dBm.
This paper presents a 20~25 GHz low noise amplifier that employs a transformer-based improved multi-path noise-canceling (IMNC) architecture. The proposed IMNC approach addresses key limitations of the conventional dual-path noise-canceling (DPNC) technique that employs common-source (CS) and common-gate (CG) stages to suppress each other's noise. In DPNC designs, noise from the CG stage cannot be fully canceled, and increasing CG transconductance to enhance CS-stage noise suppression results in a tradeoff between noise performance and power consumption. To overcome these limitations, the proposed IMNC architecture introduces a three-coil transformer that passively boosts the gain of the CG stage, thereby improving CS-stage noise cancellation without additional power consumption. The transformer also provides an additional noise-canceling path that enables partial self-cancellation of CG stage noise. These improvements lead to better noise performance and power efficiency compared to the conventional DPNC approach. Fabricated in a 40 nm complementary metal oxide semiconductor (CMOS) process, the proposed low noise amplifier achieves a peak gain of 14.5 dB, a 3 dB bandwidth of 5.1 GHz spanning 20 to 25 GHz, and a minimum noise figure (NF) of 2.0 dB, while consuming 22.4 mW of power and occupying a core area of 0.16 mm2.
A 70.3~86.6 GHz low-noise amplifier (LNA) was investigated, which can be applied simultaneously to E-band communication and 77 GHz automotive radar systems. The LNA employs a three-stage differential architecture to suppress common-mode noise. In the input stage, a source-gate-coupled-transformer-based noise-cancellation and equivalent transconductance enhancement technique is implemented to simultaneously reduce noise and boost gain. Together with a single-ended-to-differential balun, the input network achieves both impedance and optimal noise matching. The intermediate stage uses a common-source configuration with neutralization capacitors to improve gain and stability, while the output stage employs a cascode topology with a common-gate short-circuit technique and dual neutralization capacitors scheme to mitigate parasitic effects and further enhance gain and stability. Additionally, an inductor is introduced between the source of the common-gate transistor and the drain of the common-source transistor to alleviate parasitic effects and extend the cutoff frequency. Simulation results demonstrate that the proposed LNA achieves a peak gain of 22.54 dB, a 3 dB bandwidth covering 70.3~86.6 GHz, and a minimum noise figure of 5.48 dB, with noise variation less than 0.69 dB across the operating band. The input and output return losses are both better than those at –8.5 dB, and the input 1 dB compression point (IP1dB) is –16.39 dBm.
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