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    High-efficiency, tri-mode, low-EMI synchronized buck DC-DC converter
    Shixiang DING, Songmao HAO, Chunqi SHI
    J* E* C* N* U* N* S*    2026, 2026 (2): 82-94.   DOI: 10.3969/j.issn.1000-5641.2026.02.008
    Abstract （48）   HTML （2）    PDF（pc） （3477KB）（16）       Save

    This paper presents a tri-mode buck converter designed using the 55 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, which offers a peak efficiency of 92.95% for low-EMI applications. The converter employs a seamless transition between pulse-width modulation (PWM), pulse-frequency modulation (PFM), and pulse-skip modulation (PSM) modes under various load conditions, which optimizes the efficiency and ripple performance from light to heavy loads. By implementing spread-spectrum frequency modulation with 35% frequency dithering, the converter reduces the peak of the output voltage spectrum by 22 dB, thus significantly reducing the EMI emission spectrum.

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    A wide-range high-efficiency peak-current-mode Buck DC-DC converter based on adaptive quadratic slope compensation
    Xuyang LI, Xiaodi ZHOU, Yanwen WU, Songmao HAO, Chunqi SHI
    J* E* C* N* U* N* S*    2026, 2026 (2): 95-107.   DOI: 10.3969/j.issn.1000-5641.2026.02.009
    Abstract （36）   HTML （2）    PDF（pc） （1885KB）（13）       Save

    This paper presents a high-efficiency peak current-mode (PCM) Buck DC-DC converter utilizing adaptive quadratic slope compensation. The proposed design generates tailored adaptive slope voltages across wide ranges of input voltage, output voltage, load current, and switching frequency, resulting in excellent transient performance. Fabricated in a 55 nm BCD process, the chip occupies a compact core area of only 0.186 mm2. It supports an input voltage range of 3.7~5.0 V, an output voltage range of 1.5~3.5 V, a maximum load current of 1.00 A, and a switching frequency configurable from 1.0 MHz to 4.0 MHz. The converter achieves a peak efficiency of 96.0%, maintains efficiency above 93.0% at 1.00 A output current, and delivers over 90.0% efficiency across the load range from 0.03 A to 1.00 A. Post-layout simulation results confirm that the proposed compensation technique exhibits strong adaptability under varied application configurations.

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    High-energy-efficiency 12b 200 MS/s pipeline SAR ADC based on ring amplifier
    Shouxiang HAN, Junhao PU, Zhiwei HU, Runxi ZHANG
    J* E* C* N* U* N* S*    2026, 2026 (2): 108-116.   DOI: 10.3969/j.issn.1000-5641.2026.02.010
    Abstract （54）   HTML （2）    PDF（pc） （2194KB）（23）       Save

    This study proposes a 12b 200 MS/s pipeline successive approximation analog-to-digital converter (Pipeline SAR ADC) for 5G and Wi-Fi 6E wireless communication applications. To address drawbacks such as slow speed and high power consumption in the residue amplifiers of conventional Pipeline ADC, a pseudo-differential switched-capacitor amplifier based on a self-biased ring amplifier is designed. This design incorporates a reference voltage-halving technique in the second stage to reduce the system power consumption and enhance the overall speed. For traditional gate-bootstrapped switches, optimizations for speed and partial compensation of clock feedthrough effects are implemented. In addition, a set-reset (SR) latched data register is proposed to accelerate the logic circuitry of the SAR ADC. The ADC is designed using a 55 nm CMOS process with a core area of 0.182 mm2. The simulation results show that at 27℃ and a 1.2 V supply voltage, the signal-to-noise distortion ratio (SNDR) was 72.93 dB, the power consumption was 9.28 mW, and the Schreier figure of merit (FoMS) was 173.25 dB, at an input signal frequency of 97.85 MHz.

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    Design of a high-precision third-order NS SAR ADC for audio applications
    Nannan GENG, Jikun WANG, Shouxiang HAN, Chunqi SHI
    J* E* C* N* U* N* S*    2026, 2026 (2): 117-127.   DOI: 10.3969/j.issn.1000-5641.2026.02.011
    Abstract （51）   HTML （2）    PDF（pc） （1420KB）（19）       Save

    This paper proposes the design of a high-precision third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) for audio applications. The NS effect of passive NS circuits deteriorates owing to gain loss. In response, a cascaded integral feed-forward (CIFF) active NS loop is designed. To mitigate the impact of integrator nonlinearity on the ADC, a primary-auxiliary dual-path high-linearity source follower structure is proposed. This source follower buffers the residual voltage onto the integration capacitor, ultimately achieving third-order NS performance. A mismatch error shaping (MES) technique is incorporated to mitigate nonlinearities induced by digital-to-analog converter (DAC) mismatches. Fabricated in a 55 nm CMOS process, the ADC core occupies approximately 0.25 mm2. Post-layout simulation results demonstrate that under a 1.8 V supply voltage at 40℃, while operating at a sampling frequency of 8 MS/s with a bandwidth of 125 kHz and consuming 10.83 mW of power, the ADC achieves an effective number of bits (ENOB) of 15.14 and a signal-to-noise and distortion ratio (SNDR) of 92.92 dB with a Schreier figure of merit (FoMS) of 163.54 dB.

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