Journal of East China Normal University(Natural Sc ›› 2006, Vol. 2006 ›› Issue (4): 11-15.

• Article • Previous Articles     Next Articles

Design of I2CBus Interface Based on Spartan II XC2S100(Chinese)

HU Wen-jing1,2, LI Wai-yun1, LIU Jing-gao1   

  1. 1.School of Information Science and Technology, East China Normal University, Shanghai 200062,China; 2.Department of Physics and Electronics Information, Hunan Institute of Science and Technology, Yueyang Hunan 414006,China
  • Received:2004-10-26 Revised:2004-12-30 Online:2006-07-25 Published:2006-07-25
  • Contact: LIU Jing-gao

Abstract: The protocol and principle of I2C-Bus were introduced. The framework of I2CBus based on FPGA was proposed. The idea of nesting state-machine of complicated timing-circuit and the hardware description of I2C-Bus interface by Verilog HDL were presented. The simulation of designing under the Xilinx ISE 6.1i development platform combined with ModelSim SE 5.7 was made and the operation on I2C device based on Spartan II XC2S100 was implemented.

Key words: XC2S100, I2C-Bus, Verilog HDL, nesting state machine, Field Programmable Gate Array, XC2S100, I2C-Bus, Verilog HDL, nesting state machine

CLC Number: