A 20~25 GHz transformer-based improved multi-path noise-canceling low noise amplifier

doi:10.3969/j.issn.1000-5641.2026.02.006

Abstract

Abstract:

This paper presents a 20~25 GHz low noise amplifier that employs a transformer-based improved multi-path noise-canceling (IMNC) architecture. The proposed IMNC approach addresses key limitations of the conventional dual-path noise-canceling (DPNC) technique that employs common-source (CS) and common-gate (CG) stages to suppress each other's noise. In DPNC designs, noise from the CG stage cannot be fully canceled, and increasing CG transconductance to enhance CS-stage noise suppression results in a tradeoff between noise performance and power consumption. To overcome these limitations, the proposed IMNC architecture introduces a three-coil transformer that passively boosts the gain of the CG stage, thereby improving CS-stage noise cancellation without additional power consumption. The transformer also provides an additional noise-canceling path that enables partial self-cancellation of CG stage noise. These improvements lead to better noise performance and power efficiency compared to the conventional DPNC approach. Fabricated in a 40 nm complementary metal oxide semiconductor (CMOS) process, the proposed low noise amplifier achieves a peak gain of 14.5 dB, a 3 dB bandwidth of 5.1 GHz spanning 20 to 25 GHz, and a minimum noise figure (NF) of 2.0 dB, while consuming 22.4 mW of power and occupying a core area of 0.16 mm².

Key words: complementary metal oxide semiconductor (CMOS), low noise amplifier, noise cancellation, transconductance boosting

CLC Number:

TN43

Ziyao WANG, Yuri LU, Runxi ZHANG. A 20~25 GHz transformer-based improved multi-path noise-canceling low noise amplifier[J]. J* E* C* N* U* N* S*, 2026, 2026(2): 59-70.

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数据来源	工艺	频率/GHz	3 dB带宽/GHz	增益/dB	噪声系数/dB	IP1dB /dBm	功耗/mW	核心面积/mm²
TMTT 2019^[25]	40 nm RFSOI	28.5	11.0	8.5	2.7	–15.0	28.0	0.25
RFIC 2019^[26]	65 nm CMOS	28.7	7.6	18.3	3.3	–24.0	20.7	0.11
TCAS-II 2021^[27]	45 nm CMOS	23.5	5.0	9.5	4.5	–12.0	20.7	0.69
TCAS-I 2022^[28]	28 nm CMOS	27.1	4.8	19.1	3.3	–8.7	25.5	0.17
MWCL 2024^[29]	65 nm CMOS	28.0	7.5	16.6	4.1	–12.1	26.4	0.10
TMTT 2024^[30]	65 nm CMOS	39.0	20.0	21.5	2.2	–17.2	22.0	0.16
本文	40 nm CMOS	22.5	5.1	14.5	2.0	–8.9	22.4	0.16